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[Other resource] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2459435 | Author: 陈东平 | Hits:

[SourceCode] altera sdram controller

Description: altera sdram controller vhdl
Platform: | Size: 2365413 | Author: langzhongfeilang@126.com | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2458624 | Author: 陈东平 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437248 | Author: kevin | Hits:

[Other] AlteraSDRAMControllerWhitePaper

Description: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Platform: | Size: 701440 | Author: wood | Hits:

[MiddleWare] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98304 | Author: | Hits:

[Embeded-SCM Develop] SDRAM

Description: SDRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Platform: | Size: 1571840 | Author: 李大同 | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[Compress-Decompress algrithms] rd1010_source_code

Description: 使用FPGA做SDRAM控制器 -SDRAM controller using FPGA so
Platform: | Size: 357376 | Author: | Hits:

[Software Engineering] sdrsdramuse

Description: 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。-ALTERA s FPGA on a how to achieve the guidance of SDR SRAM articles. Great guiding significance.
Platform: | Size: 701440 | Author: kurt | Hits:

[VHDL-FPGA-Verilog] H1wQqGvI

Description: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Platform: | Size: 777216 | Author: 黄辉辉 | Hits:

[ARM-PowerPC-ColdFire-MIPS] SDRAM

Description: ALTERA SDR AM Controller White Paper
Platform: | Size: 658432 | Author: 付茗 | Hits:

[VHDL-FPGA-Verilog] source

Description: SDRAM通用接口程序，和Altera所给标准一致-SDRAM generic interface procedures, and to the standards by Altera
Platform: | Size: 14336 | Author: 王并 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[SCM] DE2_70_User_manual_v101

Description: Altera DE2-70开发板的使用手册-Altera DE2-70 development board manual
Platform: | Size: 3685376 | Author: 桑圣锋 | Hits:

[VHDL-FPGA-Verilog] AlteraSdramIP

Description: Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
Platform: | Size: 781312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Platform: | Size: 776192 | Author: 费尔德 | Hits:

[VHDL-FPGA-Verilog] AlteraSDR-SDRAM

Description: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Platform: | Size: 811008 | Author: machenghai | Hits:

[VHDL-FPGA-Verilog] AlteraSdramIP

Description: Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
Platform: | Size: 723968 | Author: hu71992 | Hits:
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